38K2 datasheet(191/358 Pages) RENESAS

191 / 358 page

2.4 Serial I/O

Rev.2.00

Oct 15, 2006

page 42 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

Fig. 2.4.5 Structure of UART control register

Fig. 2.4.4 Structure of Serial I/O control register

Serial I/O control register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Serial I/O control register (SIOCON) [Address : 0FE016]

0 : System clock

1 : System clock/4

BRG count source

selection bit (CSS)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

Transmit interrupt

source selection bit (TIC)

Transmit enable bit (TE)

Receive enable bit (RE)

Serial I/O enable bit

(SIOE)

SRDY output enable bit

(SRDY)

0 : P43 pin operates as ordinary I/O pin

1 : P43 pin operates as SRDY output pin

0 : Interrupt when transmit buffer has emptied

1 : Interrupt when transmit shift operation is

completed

Serial I/O synchronous

clock selection bit (SCS)

• In clock synchronous serial I/O

0 : BRG output divided by 4

1 : External clock input

• In UART

0 : BRG output divided by 16

1 : External clock input divided by 16

Serial I/O mode selection bit

(SIOM)

0 : Clock asynchronous(UART) serial I/O

1 : Clock synchronous serial I/O

0 : Serial I/O disabled

(pins P40 to P43 operate as ordinary I/O pins)

1 : Serial I/O enabled

(pins P40 to P43 operate as serial I/O pins)

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

UART control register (UARTCON) [Address : 0FE116]

Nothing is allocated for these bits. These are write disabled bits.

When these bits are read out, the contents are “1”.

UART control register

Character length selection bit

(CHAS)

Parity enable bit

(PARE)

Stop bit length selection bit

(STPS)

Parity selection bit

(PARS)

0 : 8 bits

1 : 7 bits

0 : Parity checking disabled

1 : Parity checking enabled

0 : 1 stop bit

1 : 2 stop bits

0 : Even parity

1 : Odd parity

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the contents are “0”.

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