SH7014 datasheet(663/754 Pages) RENESAS

663 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 629 of 716

REJ09B0398-0500

MTU

Timer Control Register 1 (TCR1)

H'FFFF8280

8/16/32

Bit

Item

Bit name

―

CCLR1

CCLR0

CKEG1

CKEG0

TPSC2

TPSC1

TPSC0

Initial value

R/W

Bit

Name

Value

Description

TCNT clear disabled

(initial value)

TCNT is cleared by TGRA compare-match or input

capture

TCNT is cleared by TGRB compare-match or input

capture

7 to 5

Counter Clear 2 to 0

(Reserved*

2, CCLR1, CCLR0)

Synchronizing clear: TCNT is cleared in

synchronization with clear of other channel counters

operating in sync*

Count on rising edges

(initial value)

Count on falling edges

4, 3

Clock Edge 1, 0

(CKEG1, CKEG0)*

Count on both rising and falling edges

Internal clock: count with

φ/1

(initial value)

Internal clock: count with

φ/4

Internal clock: count with

φ/16

Internal clock: count with

φ/64

External clock: count with the TCLKA pin input

External clock: count with the TCLKB pin input

Internal clock: count with

φ/256

2 to 0*

Timer Prescaler 2 to 0

(TPSC2 to TPSC0)

Count with the TCNT2 overflow/underflow

Notes:

1. Setting the SYNC bit of the TSYR to 1 sets the synchronization.

2. The bit 7 of channels 1 is reserved. It always reads 0, and cannot be modified.

3. X: 0 or 1, don't care.

4. These settings are ineffective when channel 1 is in phase counting mode.

5. Internal clock edge selection is effective when the input clock is

φ/4 or slower. These settings are

ignored when

φ/1, or the overflow/underflow of another channel is selected for the input clock.

SH7014 Datasheet(PDF) 663 Page - Renesas Technology Corp

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