SH7014 datasheet(665/754 Pages) RENESAS

665 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 631 of 716

REJ09B0398-0500

MTU

Timer I/O Control Register 1 (TIOR1)

H'FFFF8282

8/16/32

Bit

Item

Bit name

IOB3

IOB2

IOB1

IOB0

IOA3

IOA2

IOA1

IOA0

Initial value

R/W

Bit

Name

Value

Description

Output disabled

(initial value)

Output 0 on compare-match

Output 1 on compare-match

Initial output is 0

Toggle output on compare-

matc

Output disabled

Output 0 on compare-match

Output 1 on compare-match

TGR1B is

an output

compare

Initial output is 1

Toggle output on compare-

matc

Input capture on rising edge

Input capture on falling edge

Capture input

source is the

TIOC1B pin

Input capture on both edges

7 to 4

I/O Control B3 to B0

(IOB3 to IOB0)

TGR1B is

an output

compare

Capture input

source TGR0C

compare/match

input capture

Input capture on channel

0/TGR0C compare-

match/input capture

generation

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