SH7014 datasheet(115/754 Pages) RENESAS

115 / 754 page

6. Interrupt Controller (INTC)

Rev.5.00 Sep. 27, 2007 Page 81 of 716

REJ09B0398-0500

6.3

Description of Registers

6.3.1

Interrupt Priority Registers A to H (IPRA to IPRH)

Interrupt priority registers A to H (IPRA to IPRH) are 16-bit readable/writable registers that set

priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.

Correspondence between interrupt request sources and each of the IPRA to IPRH bits is shown in

table 6.4.

Bit:

Initial value:

R/W:

R/W

Bit:

Initial value:

R/W:

R/W

Table 6.4

Interrupt Request Sources and IPRA to IPRH

Bits

15 to 12

11 to 8

7 to 4

3 to 0

Interrupt priority register A

IRQ0

IRQ1

IRQ2

IRQ3

Interrupt priority register B

Reserved

IRQ6

IRQ7

Interrupt priority register C

DMAC0

DMAC1

Reserved

Interrupt priority register D

MTU0

MTU1

Interrupt priority register E

MTU2

Reserved

Interrupt priority register F

Reserved

SCI0

SCI1

Interrupt priority register G

A/D

Reserved

CMT0

CMT1

Interrupt priority register H

WDT, BSC

Reserved

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