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SH7014 Datasheet(PDF) 134 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 134 Page - Renesas Technology Corp |
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134 / 754 page  7. Cache Memory (CAC) Rev.5.00 Sep. 27, 2007 Page 100 of 716 REJ09B0398-0500 Idle cycle Idle cycle Idle cycle CK Internal address Address RAS CASx Data ROW COLUMN Miss-hit RAS assert extension Figure 7.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space (Normal Mode, TPC = 0, RCD = 0, No Wait) Miss-hit ROW COLUMN CS space Wait COLUMN RAS assert extension CK Internal address Address RAS CASx Data DRAM access CS space access DRAM access Miss-hit Figure 7.8 Cache Fill Timing in Case of Consecutive Cache Misses from DRAM Space (RAS Down Mode, TPC = 0, RCD = 0, No Wait) 7.4.4 Cache Hit after Cache Miss The first cache hit after a cache miss is regarded as a cache miss, and a cache fill without idle cycle generation is performed. The next hit operates as a cache hit. |
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