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SH7014 Datasheet(PDF) 131 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 131 Page - Renesas Technology Corp |
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131 / 754 page ![]() 7. Cache Memory (CAC) Rev.5.00 Sep. 27, 2007 Page 97 of 716 REJ09B0398-0500 7.3.2 Cache Data Array Read/Write Space The cache data array has a compulsory read/write (figure 7.4). Address Upper 22 bits of the data array space address (22 bits) ⎯ (2 bits) Entry address (8 bits) 31 0 21 10 9 Data Data (32 bits) 31 0 Figure 7.4 Cache Data Array Data Array Read: Designates entry address and reads out the corresponding line of data. Data Array Write: Designates entry address and writes designated data to the corresponding line. |
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