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SH7014 Datasheet(PDF) 128 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 128 Page - Renesas Technology Corp |
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128 / 754 page  7. Cache Memory (CAC) Rev.5.00 Sep. 27, 2007 Page 94 of 716 REJ09B0398-0500 7.2 Register Explanation 7.2.1 Cache Control Register (CCR) The cache control register (CCR) selects the cache enable/disable of each space. The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is not initialized by standby mode. Bit: 15 14 13 12 11 10 9 8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value: * * * * * * * * R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ CE DRAM CE CS3 CE CS2 CE CS1 CE CS0 Initial value: * * * 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W Note: * Bits 15 to 5 are undefined. Bits 15 to 5 ⎯Reserved: Reading these bits gives undefined values. The write value should always be 0. Bit 4 ⎯DRAM Space Cache Enable (CEDRAM): Selects whether to use DRAM space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 4 CEDRAM Description 0 DRAM space cache disabled (initial value) 1 DRAM space cache enabled |
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