| Electronic Components Datasheet Search |
|
SH7014 Datasheet(PDF) 127 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7014 Datasheet(HTML) 127 Page - Renesas Technology Corp |
|
127 / 754 page ![]() 7. Cache Memory (CAC) Rev.5.00 Sep. 27, 2007 Page 93 of 716 REJ09B0398-0500 7.1.3 Register Configuration The cache has one register, which can be used to control the enabling or disabling of each cache space. The register configuration is shown in table 7.1. Table 7.1 Register Configuration Name Abbreviation R/W Initial Value Address Access Size (Bits) Cache control register CCR R/W H'0000* H'FFFF8740 8, 16, 32 Note: * Bits 15 to 5 are undefined. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |