SH7014 datasheet(157/754 Pages) RENESAS

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SH7014 Datasheet(PDF) 157 Page - Renesas Technology Corp

Part #	SH7014

Description	32-Bit RISC Microcomputer

PDF	754 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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157 / 754 page

8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 123 of 716

REJ09B0398-0500

8.3

Accessing Ordinary Space

A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM

direct connections.

8.3.1

Basic Timing

Figure 8.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are

performed in 2 states.

Address

CSn

Read

Write

Data

WRx

Data

Figure 8.3 Basic Timing of Ordinary Space Access

During a read, irrespective of operand size, all bits in the data bus width for the access space

(address) are fetched by the LSI on

RD, using the required byte locations.

During a write, the following signals are associated with transfer of these actual byte locations:

WRH (bits 15 to 8) and WRL (bits 7 to 0).

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