SH7014 datasheet(160/754 Pages) RENESAS

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SH7014 Datasheet(PDF) 160 Page - Renesas Technology Corp

Part #	SH7014

Description	32-Bit RISC Microcomputer

PDF	754 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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160 / 754 page

8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 126 of 716

REJ09B0398-0500

8.3.3

CS Assert Period Extension

Idle cycles can be inserted to prevent extension of the

RD signal or WRx signal assert period

beyond the length of the

CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This

allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. T

h and Tf

cycles are added respectively before and after the ordinary cycle. Only

CSn is asserted in these

cycles;

RD and WRx signals are not. Further, data is extended up to the T

f cycle, which is

effective for gate arrays and the like, which have slower write operations.

Read

Write

Address

CSn

Data

WRx

Data

DACK

Figure 8.6

CS Assert Period Extension Function

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