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SH7014 Datasheet(PDF) 163 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 163 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 129 of 716
REJ09B0398-0500
8.4.3
Wait State Control
Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1,
DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and
writes. The timing with waits inserted is shown in figures 8.8 through 8.11. External waits can be
inserted at the time of software waits 2, 3. The sampling location is the same as that of ordinary
space: at one cycle before the T
c2 cycle clock rise. Wait cycles are extended by external waits.
Tp
Tr
Tc1
Tcw1
Tc2
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row
Column
Figure 8.8 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, One Wait)



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