SH7014 datasheet(169/754 Pages) RENESAS

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8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 135 of 716

REJ09B0398-0500

8.4.5

Refresh Timing

The bus state controller is equipped with a function to control refreshes of DRAM. CAS-before-

RAS (CBR) refresh or self-refresh can be selected by setting the RTCSR's RMD bit.

CAS-before-RAS Refresh: For CBR refreshes, set the RCR's RMD bit to 0 and the RFSH bit to

1. Also write the values in RTCNT and RTCOR necessary to fulfill the refresh interval prescribed

for the DRAM being used. When a clock is selected with the CKS2 to CKS0 bits of the RSTCR,

RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared

to the RTCOR value and a CBR refresh is performed when the two match. RTCNT is cleared at

that time and the count starts again. Figure 8.15 shows the timing for the CBR refresh operation.

The number of RAS assert cycles in the refresh cycle is set by the TRAS1, TRAS0 bits of the

DCR.

CASx

RAS

TRp

TRr1

TRr2

TRc

Figure 8.15 CAS-Before-RAS Refresh Timing (TRAS1, TRAS0 = 0, 0)

Self-Refresh: When both the RMD and RFSH bits of the RTCSR are set to 1, the

CAS signal and

RAS signal are output and the DRAM enters self-refresh mode, as shown in figure 8.16. Do not

access DRAM during self-refreshes, in order to preserve DRAM data. When performing DRAM

accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row

addresses within the time prescribed for the particular DRAM.

SH7014 Datasheet(PDF) 169 Page - Renesas Technology Corp