SH7014 datasheet(170/754 Pages) RENESAS

170 / 754 page

8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 136 of 716

REJ09B0398-0500

CASx

RAS

TRp

TRr1

TRr2

TRc

Figure 8.16 Self-Refresh Timing

8.5

Address/Data Multiplex I/O Space Access

When the BCR1 register IOE bit is set to 1, the D15 to D0 pins can be used for multiplexed

address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data

multiplexing can be directly connected to this LSI.

Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0

and 16 bit when A14 = 1.

8.5.1

Basic Timing

When the IOE bit of the BCR1 is set to 1, CS3 space becomes address/data multiplex I/O space.

When this space is accessed, addresses and data are multiplexed. When the A14 address bit is 0,

the bus size becomes 8 bit and addresses and data are input and output through the D7 to D0 pins.

When the A14 address bit is 1, the bus size becomes 16 bit and address output and data I/O occur

through the D15 to D0 pins. Access for the address/data multiplex I/O space is controlled by the

AH, RD and WRx signals.

Address/data multiplex I/O space accesses are done after a 3-cycle (fixed) address output, as an

ordinary space type access (figure 8.17).

SH7014 Datasheet(PDF) 170 Page - Renesas Technology Corp