SH7014 datasheet(206/754 Pages) RENESAS

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9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 172 of 716

REJ09B0398-0500

Bus Mode and Channel Priority Order

When a given channel is transferring in burst mode, and a transfer request is issued to channel 0,

which has a higher priority ranking, transfer on channel 0 begins immediately. Channel 1 transfer

is continued after transfer on channel 0 are completely ended, whether the channel 0 setting is

cycle steal mode or burst mode.

9.3.5

Number of Bus Cycle States and DREQ Pin Sample Timing

Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the

bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus

master. For details, see section 8, Bus State Controller.

DREQ Pin Sampling Timing and DRAK Signal: In external request mode, the DREQ pin is

sampled by either falling edge or low-level detection. When a

DREQ input is detected, a DMAC

bus cycle is issued and DMA transfer effected, at the earliest, after three states. However, in burst

mode when single address operation is specified, a dummy cycle is inserted for the first bus cycle.

In this case, the actual data transfer starts from the second bus cycle. Data is transferred

continuously from the second bus cycle. The dummy cycle is not counted in the number of

transfer cycles, so there is no need to recognize the dummy cycle when setting the DMATCR.

DREQ sampling from the second time begins from the start of the transfer one bus cycle prior to

the DMAC transfer generated by the previous sampling.

DRAK is output once for the first

DREQ sampling, irrespective of transfer mode or DREQ

detection method. In burst mode, using edge detection,

DREQ is sampled for the first cycle only,

so DRAK is also output for the first cycle only. Therefore, the

DREQ signal negate timing can be

ascertained, and this facilitates handshake operations of transfer requests with the DMAC.

Cycle Steal Mode Operations: In cycle steal mode,

DREQ sampling timing is the same

irrespective of dual or single address mode, or whether edge or low-level

DREQ detection is used.

For example, DMAC transfer begins (figure 9.9), at the earliest, three cycles from the first

sampling timing. The second sampling begins at the start of the transfer one bus cycle prior to the

start of the DMAC transfer initiated by the first sampling (i.e., from the start of the CPU(3)

transfer). At this point, if

DREQ detection has not occurred, sampling is executed every cycle

thereafter.

As in figure 9.10, whatever cycle the CPU transfer cycle is, the next sampling begins from the

start of the transfer one bus cycle before the DMAC transfer begins.

Figure 9.9 shows an example of output during DACK read and figure 9.10 an example of output

during DACK write.

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