SH7014 datasheet(222/754 Pages) RENESAS

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9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 188 of 716

REJ09B0398-0500

9.3.7

DMAC Access from CPU

The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus

master and accesses the DMAC, a minimum of three basic clock (CLK) cycles are required for

one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the

DMAC is completed in one bus cycle, a longword-size access is automatically divided into two

word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are

executed consecutively; a different bus cycle is never inserted between the two word accesses.

This applies to both write accesses and read accesses.

9.4

Examples of Use

9.4.1

Example of DMA Transfer between On-Chip SCI and External Memory

In this example, on-chip serial communication interface channel 0 (SCI0) received data is

transferred to external memory using the DMAC channel 1.

Table 9.7 indicates the transfer conditions and the setting values of each of the registers.

Table 9.7

Transfer Conditions and Register Set Values for Transfer between On-chip SCI

and External Memory

Transfer Conditions

Value

Transfer source: RDR0 of on-chip SCI0

SAR1

H'FFFF81A5

Transfer destination: external memory

DAR1

H'00400000

Transfer count: 64 times

DMATCR1

H'00000040

Transfer source address: fixed

CHCR1

H'00004D05

Transfer destination address: incremented

Transfer request source: SCI0 (RDR0)

Bus mode: cycle steal

Transfer unit: byte

Interrupt request generation at end of transfer

Channel priority ranking: 0

> 1

DMAOR

H'0001

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