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SH7014 Datasheet(PDF) 295 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 295 Page - Renesas Technology Corp |
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295 / 754 page ![]() 10. Multifunction Timer Pulse Unit (MTU) Rev.5.00 Sep. 27, 2007 Page 261 of 716 REJ09B0398-0500 Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. For DMA controller activation, clearing can also be done automatically. Figure 10.47 shows the timing for status flag clearing by the CPU. Figure 10.48 shows timing for clearing due to the DMA controller. Status flag Interrupt request signal Address Write signal φ T1 T2 TSR write cycle TSR address Figure 10.47 Timing of Status Flag Clearing by the CPU Status flag Interrupt request signal Address φ T1 T2 DMAC read cycle DMAC write cycle Source address Destination address T1 T2 Figure 10.48 Timing of Status Flag Clearing by DMAC Activation |
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