SH7014 datasheet(296/754 Pages) RENESAS

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10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 262 of 716

REJ09B0398-0500

10.7

Usage Notes

This section describes contention and other matters requiring special attention during MTU

operations.

10.7.1

Input Clock Limitations

The input clock pulse width, in the case of single edge, must be 1.5 states or greater, and 2.5 states

or greater for both edges. Normal operation cannot be guaranteed with lesser pulse widths.

In phase counting mode, the phase difference between the two input clocks and the overlap must

be 1.5 states or greater for each, and the pulse width must be 2.5 states or greater. Input clock

conditions for phase counting mode are shown in figure 10.49.

Overlap

Phase

difference

Overlap

Phase

difference

Pulse width

TCLKB

(TCLKD)

TCLKA

(TCLKC)

Notes: Phase difference and overlap: 1.5 states or greater

Pulse width: 2.5 states or greater

Figure 10.49 Phase Difference, Overlap, and Pulse Width in Phase Count Mode

10.7.2

Note on Cycle Setting

When setting a counter clearing by compare-match, clearing is done in the final state when TCNT

matches the TGR value (update timing for count value on TCNT match). The actual number of

states set in the counter is given by the following equation:

f =

(N + 1)

(f: counter frequency,

φ: operating frequency, N: value set in the TGR)

SH7014 Datasheet(PDF) 296 Page - Renesas Technology Corp