HD6433637SW datasheet(114/418 Pages) RENESAS

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5.5

Subsleep Mode

5.5.1

Transition to Subsleep Mode

The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed

while the SSBY bit in SYSCR1 is cleared to 0, LSON is set to 1, and bit TMA3 in TMA is set

to 1.

In subsleep mode, operation of on-chip peripheral modules other than timer A and timer G is

halted. As long as a minimum required voltage is applied, the contents of CPU registers and some

registers of the on-chip peripheral modules*, and the on-chip RAM contents, are retained. I/O

ports keep the same states as before the transition.

Note: * The contents of SCI3, DTMF generator registers are reset.

5.5.2

Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (timer A, timer G, IRQ

0 to IRQ4, WKP0 to WKP7) or by a

low input at the

RES pin.

Clearing by Interrupt: When an interrupt is requested, subsleep mode is cleared and interrupt

exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the

particular interrupt is disabled in the interrupt enable register.

Clearing by

RES Input: Clearing by RES input is the same as for standby mode; see 5.3.2,

Clearing Standby Mode.

HD6433637SW Datasheet(PDF) 114 Page - Renesas Technology Corp