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7641 Datasheet(PDF) 358 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 358 Page - Renesas Technology Corp |
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358 / 385 page  Rev.2.00 Aug 28, 2006 page 79 of 108 7641 Group REJ09B0336-0200 APPENDIX 3.5 Control registers USB interrupt status register 2 b7 b6 b5 b4 b3 b2 b1 b0 USB interrupt status register 2 (USBIS2 : address 5316) b 0 0 0 Name 0 Functions At reset R W 0 USB endpoint 4 OUT interrupt status flag (INTST9) 0 : Except the following conditions 1 : Set at which of the following conditions: • A packet data of endpoint 4 is successfully sent • UNDER_RUN bit of endpoint 4 is set to “1”. USB overrun/underrun interrupt status flag (INTST12) 0 : Except the following conditions 1 : Set at an occurrence of overrun / underrun (for isochronous data transfer) 0 0 USB endpoint 4 IN interrupt status flag (INTST8) Nothing arranged for these bits. Fix these bist to “0”. 1 2 ✽ ✽ ✽ 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 4 is successfully received • OVER_RUN bit of endpoint 4 is set to “1” • FORCE_STALL bit of endpoint 4 is set to “1”. 0 USB reset interrupt status flag (INTST13) 5 ✽ 0 : Except the following conditions 1 : Set at receiving of USB reset signal 0 USB resume signal interrupt status flag (INTST14) ✽ 0 : Except the following conditions 1 : Set at receiving of resume signal 0 USB suspend signal interrupt status flag (INTST15) ✽ 0 : Except the following conditions 1 : Set at receiving of suspend signal 4 0 7 ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. 3 6 Fig. 3.5.50 Structure of USB interrupt status register 2 |
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