7641 datasheet(359/385 Pages) RENESAS

359 / 385 page

Rev.2.00

Aug 28, 2006

page 80 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

Fig. 3.5.51 Structure of USB interrupt enable register 1

Nothing arranged for this bit. Fix this bit to “0”.

USB interrupt enable register 1

b7 b6 b5 b4 b3 b2 b1 b0

USB interrupt enable register 1

(USBIE1 : address 5416)

Name

Functions

At reset R W

USB endpoint 1 IN interrupt

enable bit (INTEN2)

USB endpoint 1 OUT inter-

rupt enable bit (INTEN3)

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

USB endpoint 2 OUT inter-

rupt enable bit (INTEN5)

USB endpoint 0 interrupt

enable bit (INTEN0)

USB endpoint 2 IN interrupt

enable bit (INTEN4)

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

USB endpoint 3 OUT inter-

rupt enable bit (INTEN7)

USB endpoint 3 IN interrupt

enable bit (INTEN6)

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

Nothing arranged for these bits. Fix these bits to “0”.

USB interrupt enable register 2

b7 b6 b5 b4 b3 b2 b1 b0

USB interrupt enable register 2

(USBIE2 : address 5516)

Name

Functions

At reset R W

USB endpoint 4 IN interrupt

enable bit (INTEN8)

USB endpoint 4 OUT inter-

rupt enable bit (INTEN9)

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

Nothing arranged for this bit. Fix this bit to “1”.

Nothing arranged for this bit. Fix this bit to “0”.

USB overrun/underrun

interrupt enable bit (INTEN12)

0 : Disabled

1 : Enabled

USB suspend/resume

interrupt enable bit (INTEN15)

0 : Disabled

1 : Enabled

Fig. 3.5.52 Structure of USB interrupt enable register 2

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