7641 datasheet(376/385 Pages) RENESAS

376 / 385 page

Addressing mode

ZP, X

ZP, Y

ABS

ABS, X

ABS, Y

IND

ZP, IND

IND, X

IND, Y

REL

Processor status register

OP n# OP n# OP n# OP n# OP n

# OP n# OP n#

OP n#

OP n# OP n

Addressing mode

Symbol

Function

Details

IMP

IMM

BIT, A

BIT, ZP

OP n# OP n# OP n# OP n# OP n#

OP n

7641 Group

APPENDIX

3.7 Machine instructions

Rev.2.00

Aug 28, 2006

page 100 of 108

REJ09B0336-0200

7641 Group

APPENDIX

3.7 Machine instructions

Rev.2.00

Aug 28, 2006

page 101 of 108

REJ09B0336-0200

•

3 19 53

01 6

2 11 6

(Value saved in stack)

This instruction shifts either A or M one bit to

the right such that bit 7 of the result always is

set to 0, and the bit 0 is stored in C.

This instruction multiply Accumulator with the

memory specified by the Zero Page X address

mode and stores the high-order byte of the re-

sult on the Stack and the low-order byte in A.

This instruction adds one to the PC but does

no other operation.

When T = 0, this instruction transfers the con-

tents of A and M to the ALU which performs a

bit-wise “OR”, and stores the result in A.

When T = 1, this instruction transfers the con-

tents of M(X) and the M to the ALU which

performs a bit-wise OR, and stores the result

in M(X). The contents of A remain unchanged,

but status flags are changed.

M(X) represents the contents of memory

where is indicated by X.

This instruction pushes the contents of A to

the memory location designated by S, and

decrements the contents of S by one.

This instruction pushes the contents of PS to

the memory location designated by S and dec-

rements the contents of S by one.

This instruction increments S by one and

stores the contents of the memory designated

by S in A.

This instruction increments S by one and

stores the contents of the memory location

designated by S in PS.

This instruction shifts either A or M one bit left

through C. C is stored in bit 0 and bit 7 is

stored in C.

This instruction shifts either A or M one bit

right through C. C is stored in bit 7 and bit 0 is

stored in C.

This instruction rotates 4 bits of the M content

to the right.

This instruction increments S by one, and

stores the contents of the memory location

designated by S in PS. S is again incremented

by one and stores the contents of the memory

location designated by S in PCL. S is again

incremented by one and stores the contents of

memory location designated by S in PCH.

This instruction increments S by one and

stores the contents of the memory location

designated by S in PC L . S is again

incremented by one and the contents of the

memory location is stored in PC H. PC is

incremented by 1.

LSR

MUL

NOP

ORA

(Note 1)

PHA

PHP

PLA

PLP

ROL

ROR

RRF

RTI

RTS

M(S) • A

← A ✽ M(zz + X)

← S – 1

← PC + 1

When T = 0

← A V M

When T = 1

M(X)

← M(X) V M

M(S)

← A

← S – 1

M(S)

← PS

← S – 1

← S + 1

← M(S)

← S + 1

← M(S)

← S + 1

← M(S)

← S + 1

PCL

← M(S)

← S + 1

PCH

← M(S)

← S + 1

PCL

← M(S)

← S + 1

PCH

← M(S)

(PC)

← (PC) + 1

←

←C ←

→

C →

→

→C

4A 1

EA 1

09 2

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