7641 datasheet(373/385 Pages) RENESAS

373 / 385 page

Addressing mode

ZP, X

ZP, Y

ABS

ABS, X

ABS, Y

IND

ZP, IND

IND, X

IND, Y

REL

Processor status register

OP n# OP n# OP n# OP n# OP n

# OP n# OP n#

OP n#

OP n# OP n

Addressing mode

Symbol

Function

Details

IMP

IMM

BIT, A

BIT, ZP

OP n# OP n# OP n# OP n# OP n#

OP n

7641 Group

APPENDIX

3.7 Machine instructions

Rev.2.00

Aug 28, 2006

page 94 of 108

REJ09B0336-0200

7641 Group

APPENDIX

3.7 Machine instructions

Rev.2.00

Aug 28, 2006

page 95 of 108

REJ09B0336-0200

•

When T = 0, this instruction adds the contents

M, C, and A; and stores the results in A and C.

When T = 1, this instruction adds the contents

of M(X), M and C; and stores the results in

M(X) and C. When T=1, the contents of A re-

main unchanged, but the contents of status

flags are changed.

M(X) represents the contents of memory

where is indicated by X.

When T = 0, this instruction transfers the con-

tents of A and M to the ALU which performs a

bit-wise AND operation and stores the result

back in A.

When T = 1, this instruction transfers the con-

tents M(X) and M to the ALU which performs a

bit-wise AND operation and stores the results

back in M(X). When T = 1, the contents of A

remain unchanged, but status flags are

changed.

M(X) represents the contents of memory

where is indicated by X.

This instruction shifts the content of A or M by

one bit to the left, with bit 0 always being set to

0 and bit 7 of A or M always being contained in

This instruction tests the designated bit i of M

or A and takes a branch if the bit is 0. The

branch address is specified by a relative ad-

dress. If the bit is 1, next instruction is

executed.

This instruction tests the designated bit i of the

M or A and takes a branch if the bit is 1. The

branch address is specified by a relative ad-

dress. If the bit is 0, next instruction is

executed.

This instruction takes a branch to the ap-

pointed address if C is 0. The branch address

is specified by a relative address. If C is 1, the

next instruction is executed.

This instruction takes a branch to the ap-

pointed address if C is 1. The branch address

is specified by a relative address. If C is 0, the

next instruction is executed.

This instruction takes a branch to the ap-

pointed address when Z is 1. The branch

address is specified by a relative address.

If Z is 0, the next instruction is executed.

This instruction takes a bit-wise logical AND of

A and M contents; however, the contents of A

and M are not modified.

The contents of N, V, Z are changed, but the

contents of A, M remain unchanged.

This instruction takes a branch to the ap-

pointed address when N is 1. The branch

address is specified by a relative address.

If N is 0, the next instruction is executed.

This instruction takes a branch to the ap-

pointed address if Z is 0. The branch address

is specified by a relative address. If Z is 1, the

next instruction is executed.

ADC

(Note 1)

(Note 7)

AND

(Note 1)

ASL

BBC

BBS

BCC

(Note 5)

(Note 9)

BCS

(Note 5)

(Note 9)

BEQ

(Note 5)

(Note 8)

BIT

BMI

(Note 5)

(Note 8)

BNE

(Note 5)

(Note 8)

←

←0

29 2

0A 1

20i

06 5

25 3

65 3

69 2

20i

When T = 0

← A + M + C

When T = 1

M(X)

← M(X) + M + C

When T = 0

← A M

When T = 1

M(X)

← M(X) M

Ai or Mi = 0?

Ai or Mi = 1?

C = 0?

C = 1?

Z = 1?

N = 1?

Z = 0?

3.7 Machine instructions

BIT, A, R

BIT, ZP, R

(Note 4)

(Note 6)

(Note 4)

(Note 6)

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