7641 datasheet(370/385 Pages) RENESAS

370 / 385 page

Rev.2.00

Aug 28, 2006

page 91 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

Fig. 3.5.67 Structure of ROM code protect control register

ROM code protect control register

b7 b6 b5 b4 b3 b2 b1 b0

ROM code protect control register

(ROMCP : address FFC916) (Note 1)

Name

Functions

At reset R W

ROM code protect level 2

set bits (ROMCP2)

(Notes 2, 3)

Fix these bits to “1”.

b3b2

0 0 : Protect enabled

0 1 : Protect enabled

1 0 : Protect enabled

1 1 : Protect disabled

ROM code protect level 1

set bits (ROMCP1)

(Note 2)

b7b6

0 0 : Protect enabled

0 1 : Protect enabled

1 0 : Protect enabled

1 1 : Protect disabled

ROM code protect reset

bits (ROMCR) (Note 4)

b5b4

0 0 : Protect removed

0 1 : Protect set bits effective

1 0 : Protect set bits effective

1 1 : Protect set bits effective

Notes 1: This area is on the ROM in the mask ROM version.

2: When ROM code protect is turned on, the internal flash memory is protected

against readout or modification in parallel I/O mode.

3: When ROM code protect level 2 is turned on, ROM code readout by a shipment

inspection LSI tester, etc. also is inhibited.

4: The ROM code protect reset bits can be used to turn off ROM code protect level 1

and ROM code protect level 2. However, since these bits cannot be modified in

parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU

rewrite mode.

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