7641 datasheet(130/385 Pages) RENESAS

130 / 385 page

Rev.2.00

Aug 28, 2006

page 113 of 113

7641 Group

REJ09B0336-0200

HARDWARE

FUNCTIONAL DESCRIPTION SUPPLEMENT

Timing After Interrupt

The interrupt processing routine begins with the machine cycle fol-

lowing the completion of the instruction that is currently in

execution. Figure 104 shows a timing chart after an interrupt oc-

curs, and Figure 105 shows the time up to execution of the

interrupt processing routine.

Fig. 104 Timing chart after interrupt occurs

Fig. 105 Time up to execution of interrupt processing routine

PCH

PCL

S, SPS

S-2, SPS

S-1, SPS

AL, AH

Address bus

Data bus

Not used

: CPU operation code fetch cycle

(This is an internal signal which cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

SYNC

7 to 23 cycles (f(

φ) = 12 MHz, 0.583 µs to 1.92 µs)

Interrupt request occurs

Main routine

Interrupt processing routine

2 cycles

5 cycles

Waiting time for

pipeline post-

processing

Push onto

stack vector

fetch

Interrupt operation starts

0 to 16 cycles

7641 Datasheet(PDF) 130 Page - Renesas Technology Corp

7641 Datasheet(HTML) 130 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL