7641 datasheet(134/385 Pages) RENESAS

134 / 385 page

Rev.2.00

Aug 28, 2006

page 3 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.1 I/O port

2.1.2 Related registers

Fig. 2.1.2 Structure of Port Pi register

Port Pi

b7 b6 b5 b4 b3 b2 b1 b0

Port Pi (i = 0, 1, 2, 3, 5, 6, 8)

(Pi : addresses 0816, 0A16, 0C16, 0E16, 1616, 1416, 1C16)

Name

Functions

At reset R W

Port Pi1

Port Pi3

Port Pi4

Port Pi2

Port Pi5

Port Pi6

Port Pi7

Port Pi0

qIn output mode

Write •••••••• Port latch

Read •••••••• Port latch

qIn input mode

Write •••••••• Port latch

Read •••••••• Value of pin

Port P4, Port P7

b7 b6 b5 b4 b3 b2 b1 b0

Port P4, Port P7

(P4, P7 : addresses 1816, 1A16)

Name

Functions

At reset R W

Port P41 or Port P71

Port P43 or Port P73

Port P44 or Port P74

Port P42 or Port P72

Undefined

Port P40 or Port P70

Nothing is arranged for these bits. These are write disable bits. When

these bits are read out, the contents are undefined.

qIn output mode

Write •••••••• Port latch

Read •••••••• Port latch

qIn input mode

Write •••••••• Port latch

Read •••••••• Value of pin

Undefined

Fig. 2.1.3 Structure of Port P4, Port P7 registers

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