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7641 Datasheet(PDF) 276 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 276 Page - Renesas Technology Corp |
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276 / 385 page  Rev.2.00 Aug 28, 2006 page 145 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.12 Clock generating circuit Fig. 2.12.13 Initial setting of relevant registers Clock control register (address 1F16) 1 CCR 00 0 0 XIN division: f(XIN) (high-speed mode) Timer 1 (address 2416) T1 254 Set (Division ratio -1); 254 (FE16) Timer 123 mode register (address 2916) 0 T123M 0 Timer 1 count: Operating 0 0 Timer 1 count source: φ/8 Timer 2 count source: Timer 1 output Interrupt request register B (address 0316) 0 IREQB 0 Set “0” to timer 1 interrupt request bit Set “0” to timer 2 interrupt request bit Interrupt control register B (address 0616) ICONB 1 Timer 1 interrupt: Enabled 0 CPU mode register A (address 0016) 0 CPMA 001 XCIN-XCOUT oscillating 1 XIN-XOUT oscillating External clock selected as internal system clock f(XIN) selected as external clock; f(XCIN) selected at power failure Timer 1, 2 write: Write value in latch and counter 0 Timer 2 interrupt: Disbled b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 |
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