SH7018 datasheet(344/431 Pages) RENESAS

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16.5.3

Erase Block Register 1 (EBR1)

EBR1 is an 8-bit readable/writable register that specifies the flash memory erase area block by

block. EBR1 is initialized to H'00 by a power-on reset, in standby mode, when a high level is input

to the FWP pin, and when a low level is input to the FWP pin and the SWE bit in FLMCR1 is not

set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-

protected. As with EBR2, set only one bit of EBR1 (more than one bit cannot be set). If two or

more bits are set, writes to the ESU and E bits are invalid. When on-chip flash memory is

disabled, a read will return H'00, and writes are invalid.

The flash memory block configuration is shown in table 16.3.

Bit:

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Initial value:

R/W:

R/W

16.5.4

Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a power-on reset and in standby mode, when a high level is input to the FWP

pin, and when a low level is input to the FWP pin and the SWE bit of FLMCR1 is not set. When a

bit in EBR2 is set to 1, the corresponding block can be erased. The other blocks are erase-

protected. If the on-chip flash memory is disabled, a read will return H'00, and writes are invalid.

The flash memory block configuration is shown in table 16.3.

Bit:

—

EB10

EB9

EB8

Initial value:

R/W:

R/W

• Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.

SH7018 Datasheet(PDF) 344 Page - Renesas Technology Corp