SH7018 datasheet(187/431 Pages) RENESAS

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Table 9.1

8-Bit Timer 2 Registers

Name

Abbreviation

R/W

Initial

Value

Address

Access

Size

Timer 2 control/status register

T2CSR

R/W

H'0000

H'FFFF862C

8, 16, 32

Timer 2 counter

T2CNT

R/W

H'0000

H'FFFF862E

8, 16, 32

Timer 2 constant register

T2COR

R/W

H'0000

H'FFFF8630

8, 16

9.2

9.2.1

Timer 2 Control/Status Register (T2CSR)

The timer 2 control/status register (T2CSR) is a 16-bit readable/writable* register that selects the

clock to be input to the timer 2 counter (T2CNT) and controls compare match interrupts (CMI).

T2CSR is initialized to H'0000 by a power-on reset.

Bit:

——

———

—

Initial value:

R/W:

Bit:

—

CMF

CMIE

CKS2

CKS1

CKS0

—

Initial value:

R/W:

R/W

• Bits 15 to 7—Reserved: These bits are always read as 0. The write value should always be 0.

• Bit 6—Compare Match Flag (CMF): Status flag that indicates a match between the values of

T2CNT and T2COR. The setting and clearing conditions for this flag are shown below.

Bit 6: CMF

Description

[Clearing condition]

Cleared by reading T2CSR when CMF = 1, then writing 0 in CMF (Initial value)

[Setting condition]

Set when T2CNT = T2COR*

Note: * When T2CNT and T2COR still contain their initial values (when the initial values have not

been changed or when the T2CNT value has not been incremented), CMF is not set even

though the T2CNT and T2COR values are the same (H'0000).

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