SH7018 datasheet(188/431 Pages) RENESAS

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• Bit 5—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests

initiated by the CMF flag when set to 1 in T2CSR.

Bit 5: CMIE

Description

Interrupt request by CMF flag disabled

(Initial value)

Interrupt request by CMF flag enabled

• Bits 4 to 2—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of seven internal clock

sources, obtained by dividing the system clock (

φ), for input to T2CNT.

Bit 4: CKS2

Bit 3: CKS1

Bit 2: CKS0

Description

Up-count stopped

(Initial value)

φ/2

φ/8

φ/32

100

φ/128

φ/512

φ/2048

φ/4096

• Bits 1 and 0—Reserved: These bits are always read as 0. The write value should always be 0.

9.2.2

Timer 2 Counter (T2CNT)

The timer 2 counter (T2CNT) is a 16-bit readable/writable register used as an 8-bit up-counter.

T2CNT increments on the internal clock selected by bits CKS2 to CKS0 in T2CSR. The T2CNT

value can be read or written by the CPU at all times. When the T2CNT value matches the value in

the timer 2 constant register (T2COR), T2CNT is cleared to H'0000 and the CMF flag is set to 1 in

T2CSR. If the CMIE bit in T2CSR is set to 1 at this time, a compare match interrupt (CMI) is

generated.

Bits 15 to 8 are reserved and have no counter function. These bits are always read as 0. The write

value should always be 0.

T2CNT is initialized to H'0000 by a power-on reset.

SH7018 Datasheet(PDF) 188 Page - Renesas Technology Corp