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SH7018 Datasheet(PDF) 190 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 190 Page - Renesas Technology Corp |
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190 / 431 page  174 9.3 Operation 9.3.1 Cyclic Count Operation When a clock is selected with bits CKS2 to CKS0 in the T2CSR register, the T2CNT counter starts incrementing on the selected clock. When the T2CNT counter value matches the value in the timer 2 constant register (T2COR), the T2CNT counter is cleared to H'00, and the CMF flag is set to 1 in the T2CSR register. If the CMIE bit in T2CSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The T2CNT counter then starts incrementing again from H'00. The compare match counter operation is shown in figure 9.2. T2CNT value T2COR H'00 Counter cleared by T2COR compare match Time Figure 9.2 Counter Operation 9.3.2 T2CNT Count Timing Any of seven internal clocks ( φ/2, φ/8, φ/32, φ/128, φ/512, φ/2048, or φ/4096) divided from the system clock (CK) can be selected with bits CKS2 to CKS0 in T2CSR. The count timing is shown in figure 9.3. CK Internal clock T2CNT input clock T2CNT N – 1 N N + 1 Figure 9.3 Count Timing |
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