SH7018 datasheet(209/431 Pages) RENESAS

209 / 431 page

193

• Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the

system clock (

φ).

Description

Bit 2: CKS2 Bit 1: CKS1

Bit 0: CKS0

Clock Source

Overflow Interval*

(

φφφφ = 20.0 MHz)

φ/2 (Initial value)

25.6 µs

φ/64

819.2 µs

φ/128

1.6384 ms

φ/256

3.2768 ms

φ/512

6.5536 ms

φ/1024

13.1072 ms

φ/4096

52.4288 ms

φ/8192

104.8576 ms

Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an

overflow occurs.

11.2.3

Reset Control/Status Register (RSTCSR)

The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers

in that it is more difficult to write. See section 11.2.4, Register Access, for details.) It controls

output of the internal reset signal generated by timer counter (TCNT) overflow and selects the

internal reset signal type. RSTCR is initialized to H'1F by input of a reset signal from the

RES pin,

but is not initialized by the internal reset signal generated by the overflow of the WDT. It is

initialized to H'1F in standby mode.

Bit:

WOVF

RSTE

—

Initial value:

R/W:

R/(W)*

R/W

RRR

Note:

Only 0 can be written in bit 7 to clear the flag.

• Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that the TCNT has overflowed

(H'FF to H'00) in the watchdog timer mode. It is not set in the interval timer mode.

SH7018 Datasheet(PDF) 209 Page - Renesas Technology Corp

SH7018 Datasheet(HTML) 209 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL