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SH7018 Datasheet(PDF) 211 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 211 Page - Renesas Technology Corp |
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211 / 431 page ![]() 195 Writing to the RSTCSR: The RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 11.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. H'A5 H'FFFF8612 Address: Writing 0 to the WOVF bit 15 8 7 0 H'00 H'5A H'FFFF8612 Address: Writing to the RSTE and RSTS bits 15 8 7 0 Write data Figure 11.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR, H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR. 11.3 Operation 11.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/ IT and TME bits of the TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if RSTE of RSTCSR is set to 1 and a problem such as system runaway occurs, the value of TCNT is not overwritten and an overflow results. This causes WDT to generate an internal reset signal for the chip. The internal reset signal is output for 512 φ clock cycles. Figure 11.4 shows the timing. When a watchdog overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit is cleared to 0. The following are not initialized a WDT reset signal: |
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