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SH7018 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 431 page ![]() 199 11.4 Notes on Use 11.4.1 TCNT Write and Increment Contention If a timer counter (TCNT) increment clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 11.8). CK Address Internal write signal TCNT input clock TCNT NM TCNT address Counter write data T1 T2 T3 TCNT write cycle Figure 11.8 Contention between TCNT Write and Increment 11.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 11.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. 11.4.4 Internal Reset With the Watchdog Timer If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a TCNT overflow occurs, but the TCNT and TCSR in the WDT will reset. |
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