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SH7018 Datasheet(PDF) 219 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 219 Page - Renesas Technology Corp |
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219 / 431 page ![]() 203 12.1.4 Register Configuration Table 12.2 summarizes the SCI1 internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 12.2 Registers Name Abbreviation R/W Initial Value Address* 1 Access Size Serial mode register SMR1 R/W H'00 H'FFFF81B0 8, 16 Bit rate register BRR1 R/W H'FF H'FFFF81B1 8, 16 Serial control register SCR1 R/W H'00 H'FFFF81B2 8, 16 Transmit data register TDR1 R/W H'FF H'FFFF81B3 8, 16 Serial status register SSR1 R/(W)* 2 H'84 H'FFFF81B4 8, 16 Receive data register RDR1 R H'00 H'FFFF81B5 8, 16 Notes: 1. Do not attempt to access empty addresses. 2. The only value that can be written is a 0 to clear the flags. 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR1) The receive shift register (RSR1) receives serial data. Data input at the RxD pin is loaded into the RSR1 in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the RDR1. The CPU cannot read or write the RSR1 directly. Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — 12.2.2 Receive Data Register (RDR1) The receive data register (RDR1) stores serial receive data. The SCI1 completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR1) into the RDR1 for storage. The RSR1 is then ready to receive the next data. This double buffering allows the SCI1 to receive data continuously. The CPU can read but not write the RDR1. The RDR is initialized to H'00 by a power-on reset or in standby mode. |
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