SH7018 datasheet(218/431 Pages) RENESAS

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12.1.2

Block Diagram

Figure 12.1 shows a block diagram of the SCI1.

Parity

generation

Parity check

External clock

Transmit/

receive control

Baud rate

generator

Clock

Internal

data bus

RxD

RDR1

TDR1

RSR1

TSR1

SSR1

SCR1

SMR1

BRR1

φ/4

φ/16

φ/64

TEI

TxI

RxI

ERI

RSR1

RDR1

TSR1

TDR1

Receive shift register

Receive data register

Transmit shift register

Transmit data register

SMR1

SCR1

SSR1

BRR1

Serial mode register

Serial control register

Serial status register

Bit rate register

TxD

SCK

SCI1

Module data bus

Figure 12.1 SCI1 Block Diagram

12.1.3

Pin Configuration

Table 12.1 summarizes the SCI1 pins by channel.

Table 12.1

SCI1 Pins

Pin Name

Abbreviation

Input/Output

Function

Serial clock pin

SCK

Input/output

SCI1 clock input/output

Receive data pin

RxD

Input

SCI1 receive data input

Transmit data pin

TxD

Output

SCI1 transmit data output

SH7018 Datasheet(PDF) 218 Page - Renesas Technology Corp

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