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SH7018 Datasheet(PDF) 217 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 217 Page - Renesas Technology Corp |
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217 / 431 page ![]() 201 Section 12 Serial Communication Interface (SCI1) 12.1 Overview The SH7018 has a serial communication interface (SCI1) with one channel. The SCI supports asynchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 Features • Select asynchronous or clock synchronous as the serial communications mode. Asynchronous mode: Serial data communications are synched by start-stop in character units. The SCI1 can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs a standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. Data length: seven or eight bits Stop bit length: one or two bits Parity: even, odd, or none Multiprocessor bit: one or none Receive error detection: parity, overrun, and framing errors Break detection: by reading the RxD level directly when a framing error occurs Clock synchronous mode: Serial data transfer is synchronized with the clock. This permits serial data communications with other LSI devices equipped with a clock synchronous communications function. One serial data communications format is supported. Number of data bits: 8 Receive error detection: Over-line error detection • Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. • On-chip baud rate generator with selectable bit rates. • Internal transmit/receive clock source: baud rate generator (internal). • Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. |
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