SH7018 datasheet(299/431 Pages) RENESAS

299 / 431 page

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14.3

14.3.1

Port A IO Register L (PAIORL)

Port A IO register L (PAIORL) is a 16-bit readable/writable register that selects the input/output

direction of the pins in port A. The bits of this register correspond to the various pins. PAIORL is

enabled when the port A pins function as general input/output (PA15 to PA0) or serial clock

(SCK) pins, and disabled otherwise.

When the port A pins function as PA15 to PA0 or SCK, a pin becomes an output when the

corresponding bit in PAIORL is set to 1, and an input when the bit is cleared to 0.

PAIORL is initialized to H'0000 by an external power-on reset. However, it is not initialized by a

WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.

Bit:

PA15IOR PA14IOR

—

PA12IOR PA11IOR PA10IOR PA9IOR

PA8IOR

Initial value:

R/W:

R/W

Bit:

PA7IOR

PA6IOR

PA5IOR

PA4IOR

PA3IOR

PA2IOR

PA1IOR

PA0IOR

Initial value:

R/W:

R/W

14.3.2

Port A Control Registers L1 and L2 (PACRL1, PACRL2)

Port A control registers L1 and L2 (PACRL1, PACRL2) are 16-bit readable/writable registers that

select the functions of the pins in port A.

PACRL1 is initialized to H'4000 by an external power-on reset. PACRL2 is initialized to H'0000

by an external power-on reset. However, they are not initialized by a WDT reset, in standby mode,

or in sleep mode. In these cases they retain their previous data.

SH7018 Datasheet(PDF) 299 Page - Renesas Technology Corp