SH7018 datasheet(319/431 Pages) RENESAS

319 / 431 page

303

15.2.2

Port A Data Register L (PADRL)

Port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data. The

bits of this register correspond to the various pins.

When a pin functions as a general output, if a value is written to PADRL, that value is output

directly from the pin, and if PADRL is read, the register value is returned directly regardless of the

pin state.

When a pin functions as a general input, if PADRL is read the pin state, not the register value, is

returned directly. If a value is written to PADRL, that value is written to PADRL but it does not

affect the pin state. Table 15.2 summarizes the port A data register read/write operations.

PADRL is initialized by an external power-on reset. However, it is not initialized by a WDT reset,

in standby mode, or in sleep mode.

Bit:

PA15DR PA14DR

—

PA12DR PA11DR PA10DR

PA9DR

PA8DR

Initial value:

R/W:

R/W

Bit:

PA7DR

PA6DR

PA5DR

PA4DR

PA3DR

PA2DR

PA1DR

PA0DR

Initial value:

R/W:

R/W

Table 15.2

Port A Data Register (PADR) Read/Write Operations

PAIOR

Pin Function

Read

Write

General input

Pin state

Value is written to PADR, but does not affect

pin state

Other than general input

Pin state

Value is written to PADR, but does not affect

pin state

General output

PADR value

Write value is output from pin

Other than general output

PADR value

Value is written to PADR, but does not affect

pin state

SH7018 Datasheet(PDF) 319 Page - Renesas Technology Corp

SH7018 Datasheet(HTML) 319 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL