SH7052 datasheet(576/919 Pages) RENESAS

576 / 919 page

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Message Reception and Interrupts:

1. Message reception CRC check

When a message is received, a CRC check is performed automatically (by hardware). If the

result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of

whether or not the message can be received.

2. Data frame reception

If the received message is confirmed to be error-free by the CRC check, etc., the identifier in

the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive

message are compared, and if a complete match is found, the message is stored in the mailbox.

The message identifier comparison is carried out on each mailbox in turn, starting with

mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at

that point, the message is stored in the matching mailbox, and the corresponding receive

complete bit (RXPR0 to RXPR15) is set in the receive complete register (RXPR). However,

when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox

comparison sequence does not end at that point, but continues with mailbox 1 and then the

remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received

by another mailbox (however, the same message cannot be stored in more than one of

mailboxes 1 to 15). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt

mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask

CPU.

3. Remote frame reception

Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A

remote frame differs from a data frame in that the remote reception request bit (RTR) in the

message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned

in a data frame must be stored in the data length code (DLC) in the control field.

When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote

request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox

interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the

interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can

be sent to the CPU.

SH7052 Datasheet(PDF) 576 Page - Renesas Technology Corp