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SH7052 Datasheet(PDF) 577 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 577 Page - Renesas Technology Corp |
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577 / 919 page  551 4. Unread message reception When the identifier in a mailbox matches a receive message, the message is stored in the mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding bit (UMSR0 to UMSR15) is set in the unread message register (UMSR). In overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 15.10 shows a flowchart of unread message overwriting. UMSR = 1 IRR9 = 1 Unread message overwrite IMR9 = 1? End Yes Interrupt to CPU Clear IRR9 Message control/message data read No : Settings by user : Processing by hardware Figure 15.10 Unread Message Overwrite Flowchart |
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