SH7052 datasheet(579/919 Pages) RENESAS

579 / 919 page

553

HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master

control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is

delayed until the bus becomes idle.

Either of the following methods of clearing HCAN sleep mode can be selected by making a setting

in the MCR7 bit.

1. Clearing by software

2. Clearing by CAN bus operation

Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus

communication is enabled again.

Clearing by Software: Clearing by software is performed by having the CPU write 0 to MCR5.

Clearing by CAN Bus Operation: Clearing by CAN bus operation occurs automatically when

the CAN bus performs an operation and this change is detected. In this case, the first message is

not received in the message box; normal reception starts with the second message. When a change

is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set

in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register

(IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU.

SH7052 Datasheet(PDF) 579 Page - Renesas Technology Corp