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SH7052 Datasheet(PDF) 253 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 253 Page - Renesas Technology Corp

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TIOR3B, TIOR4B, TIOR5B
Bit:
7
6
5
4
3
2
1
0
CCIxD
IOxD2
IOxD1
IOxD0
CCIxC
IOxC2
IOxC1
IOxC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x = 3 to 5
TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, and TIOR5B specify whether general registers
GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D are used as input capture or compare-
match registers, and also perform edge detection and output value setting. They also select
enabling or disabling of free-running counter (TCNT3 to TCNT5) clearing.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—Clear Counter Enable Flag 3B, 4B, 5B, 3D, 4D, 5D (CCI3B, CCI4B, CCI5B, CCI3D,
CCI4D, CCI5D): These bits select enabling or disabling of free-running counter (TCNT)
clearing.
Bit 7: CCIxx
Description
0
TCNT clearing disabled
(Initial value)
1
TCNT cleared on GR compare-match
xx = 3B, 4B, 5B, 3D, 4D, or 5D
TCNT is cleared on compare-match only when GR is functioning as an output compare
register.



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