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SH7052 Datasheet(PDF) 250 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 250 Page - Renesas Technology Corp |
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250 / 919 page ![]() 224 Timer I/O Control Registers 2A to 2D (TIOR2A to TIOR2D) TIOR2A Bit: 7 6 5 4 3 2 1 0 — IO2B2 IO2B1 IO2B0 — IO2A2 IO2A1 IO2A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TIOR2B Bit: 7 6 5 4 3 2 1 0 — IO2D2 IO2D1 IO2D0 — IO2C2 IO2C1 IO2C0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TIOR2C Bit: 7 6 5 4 3 2 1 0 — IO2F2 IO2F1 IO2F0 — IO2E2 IO2E1 IO2E0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TIOR2D Bit: 7 6 5 4 3 2 1 0 — IO2H2 IO2H1 IO2H0 — IO2G2 IO2G1 IO2G0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Registers TIOR2A to TIOR2D specify whether general registers GR2A to GR2H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. |
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