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SH7052 Datasheet(PDF) 255 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 255 Page - Renesas Technology Corp |
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255 / 919 page  229 • Bits 2 to 0—I/O Control 3A2 to 3A0, 4A2 to 4A0, 5A2 to 5A0, 3C2 to 3C0, 4C2 to 4C0, 5C2 to 5C0 (IO3A2 to IO3A0, IO4A2 to IO4A0, IO5A2 to IO5A0, IO3C2 to IO3C0, IO4C2 to IO4C0, IO5C2 to IO5C0): These bits select the general register (GR) function. Bit 2: IOxx2 Bit 1: IOxx1 Bit 0: IOxx0 Description 0 0 0 GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 1 0 1 output on GR compare-match 1 Toggle output on GR compare-match 1 0 0 GR is an input capture register Input capture disabled (input capture by channel 3 and 9 compare-match enabled) (In channel 3 only, GR cannot be written to) 1 Input capture in GR on rising edge at TIOxx pin (GR connot be written to) 1 0 Input capture in GR on falling edge at TIOxx pin (GR connot be written to) 1 Input capture in GR on both rising and falling edges at TIOxx pin (GR connot be written to) xx = 3A, 4A, 5A, 3C, 4C, or 5C |
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