SH7713 datasheet(430/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 390 of 860

REJ09B0288-0150

12.5.2

Normal Space Interface

Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of

the fact that mainly static RAM will be directly connected. When using SRAM with a byte-

selection pin, see section 12.5.7, Byte-Selection SRAM Interface. Figure 12.3 shows the basic

timings of normal space access. A no-wait normal access is completed in two cycles. The

signal is asserted for one cycle to indicate the start of a bus cycle.

CKIO

Note: * The waveform for DACKn is when active low is specified.

A25 to A0

RD/

D31 to D0

DACKn*

CSn

WEn(BEn)

D31 to D0

Read

Write

Figure 12.3 Normal Space Basic Access Timing (Access Wait 0)

There is no access size specification when reading. The correct access start address is output in the

least significant bit of the address, but since there is no access size specification, 32 bits are always

SH7713 Datasheet(PDF) 430 Page - Renesas Technology Corp