SH7713 datasheet(69/904 Pages) RENESAS

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Section 2 CPU

Rev.1.50 Aug. 30, 2006 Page 29 of 860

REJ09B0288-0150

2.2

Memory Map

2.2.1

Logical Address Space

The LSI supports 32-bit logical addresses and accesses system resources using the 4-Gbytes of

logical address space. User programs and data are accessed from the logical address space. The

logical address space is divided into several areas as shown in table 2.1.

P0/U0 Area: This area is called the P0 area when the CPU is in privileged mode and the U0 area

when in user mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0

areas are handled as address translatable areas.

If the cache is enabled, access to the P0 or U0 area is cached. If a P0 or U0 address is specified

while the address translation unit is enabled, the P0 or U0 address is translated into a physical

address based on translation information defined by the user.

If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in

user mode, a transition to an address error exception occurs.

P1 Area: The P1 area is defined as a cacheable but non-address translatable area. Normally,

programs executed at high speed in privileged mode, such as exception processing handlers, which

are at the core of the operating system (S), are assigned to the P1 area.

P2 Area: The P2 area is defined as a non-cacheable but non-address translatable area. A reset

processing program to be called from the reset state is described at the start address (H'A0000000)

of the P2 area. Normally, programs such as system initialization routines and OS initiation

programs are assigned to the P2 area. To access a part of an on-chip I/O, its corresponding

program should be assigned to the P2 area.

P3 Area: The P3 area is defined as a cacheable and address translatable area. This area is used if

an address translation is required for a privileged program.

P4 Area: The P4 area is defined as a control area which is non-cacheable and non-address

translatable. This area can be accessed only in privileged mode. A part of the LSI's on-chip I/O is

assigned to this area.

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