SH7713 datasheet(13/904 Pages) RENESAS

13 / 904 page

Rev.1.50 Aug. 30, 2006 Page xiii of xl

4.2.2

Exception Vector Addresses ................................................................................. 160

4.2.3

Exception Codes ................................................................................................... 160

4.2.4

Exception Request and BL Bit (Multiple Exception Prevention) ......................... 160

4.2.5

Exception Source Acceptance Timing and Priority .............................................. 161

4.3

Individual Exception Operations........................................................................................ 165

4.3.1

Resets.................................................................................................................... 165

4.3.2

General Exceptions ............................................................................................... 166

4.3.3

General Exceptions (MMU Exceptions)............................................................... 169

4.4

Exception Processing while DSP Extension Function is Valid.......................................... 172

4.4.1

Illegal Instruction Exception and Slot Illegal Instruction Exception .................... 172

4.4.2

CPU Address Error ............................................................................................... 172

4.4.3

Exception in Repeat Control Period...................................................................... 172

4.5

Usage Notes ....................................................................................................................... 179

Section 5 Memory Management Unit (MMU) ..................................................181

5.1

Role of MMU.....................................................................................................................181

5.1.1

MMU of This LSI ................................................................................................. 183

5.2

Register Descriptions ......................................................................................................... 189

5.2.1

Page Table Entry Register High (PTEH) .............................................................. 190

5.2.2

Page Table Entry Register Low (PTEL) ............................................................... 191

5.2.3

Translation Table Base Register (TTB) ................................................................ 191

5.2.4

MMU Control Register (MMUCR) ...................................................................... 191

5.3

TLB Functions ...................................................................................................................193

5.3.1

Configuration of the TLB ..................................................................................... 193

5.3.2

TLB Indexing........................................................................................................ 195

5.3.3

TLB Address Comparison .................................................................................... 196

5.3.4

Page Management Information............................................................................. 198

5.4

MMU Functions................................................................................................................. 200

5.4.1

MMU Hardware Management .............................................................................. 200

5.4.2

MMU Software Management ............................................................................... 200

5.4.3

MMU Instruction (LDTLB).................................................................................. 201

5.4.4

Avoiding Synonym Problems ............................................................................... 202

5.5

MMU Exceptions............................................................................................................... 205

5.5.1

TLB Miss Exception ............................................................................................. 205

5.5.2

TLB Protection Violation Exception .................................................................... 206

5.5.3

TLB Invalid Exception ......................................................................................... 207

5.5.4

Initial Page Write Exception ................................................................................. 208

5.5.5

MMU Exception in Repeat Loop.......................................................................... 209

5.6

Memory-Mapped TLB....................................................................................................... 211

5.6.1

Address Array ....................................................................................................... 211

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