SH7713 datasheet(29/904 Pages) RENESAS

29 / 904 page

Rev.1.50 Aug. 30, 2006 Page xxix of xl

Figure 13.9 DMA Transfer Example in Cycle-Steal Mode

(Dual Address, DREQ Low Level Detection)......................................................... 487

Figure 13.10 DMA Transfer Example in Burst Mode

(Dual Address, DREQ Low Level Detection)....................................................... 487

Figure 13.11 Bus State when Multiple Channels are Operating................................................. 489

Figure 13.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 490

Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 490

Figure 13.14 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 491

Figure 13.15 Example of DREQ Input Detection in Burst Mode Level Detection .................... 491

Figure 13.16 Example of DMA Transfer End Timing (Cycle Steal Level Detection) ............... 491

Figure 13.17 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle = 1,

Longword Access to 16-bit Device)...................................................................... 492

Section 14 Timer Unit (TMU)

Figure 14.1 TMU Block Diagram............................................................................................... 496

Figure 14.2 Setting Count Operation.......................................................................................... 501

Figure 14.3 Auto-Reload Count Operation................................................................................. 501

Figure 14.4 Count Timing when Internal Clock Is Operating .................................................... 502

Figure 14.5 UNF Set Timing ...................................................................................................... 503

Figure 14.6 Status Flag Clear Timing......................................................................................... 503

Section 15 Realtime Clock (RTC)

Figure 15.1 RTC Block Diagram................................................................................................ 506

Figure 15.2 Setting Time ............................................................................................................ 525

Figure 15.3 Reading Time .......................................................................................................... 526

Figure 15.4 Using Alarm Function ............................................................................................. 527

Figure 15.5 Example of Crystal Oscillator Circuit Connection.................................................. 528

Figure 15.6 Using Periodic Interrupt Function ........................................................................... 529

Section 16 Serial Communication Interface with FIFO (SCIF)

Figure 16.1 Block Diagram of SCIF........................................................................................... 533

Figure 16.2 Data Format in Asynchronous Communication (Example of 8-Bit Data with

Parity and 2 Stop Bits) ............................................................................................ 561

Figure 16.3 Sample the SCIF Initialization Flowchart ............................................................... 564

Figure 16.4 Sample Serial Transmission Flowchart ................................................................... 565

Figure 16.5 Example of Transmit Operation (Example of 8-Bit Data with Parity and

1 Stop Bit) ............................................................................................................... 567

Figure 16.6 Sample Serial Reception Flowchart (1)................................................................... 568

Figure 16.7 Sample Serial Reception Flowchart (2)................................................................... 569

Figure 16.8 Example of SCIF Receive Operation (Example of 8-Bit Data with Parity and

1 Stop Bit) ............................................................................................................... 571

Figure 16.9

CTS Control Operation ...........................................................................................571

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