SH7713 datasheet(32/904 Pages) RENESAS

32 / 904 page

Rev.1.50 Aug. 30, 2006 Page xxxii of xl

Figure 24.11 PLL Synchronization Settling Time when Frequency Multiplication

Ratio Modified...................................................................................................... 792

Figure 24.12 Reset Input Timing................................................................................................ 794

Figure 24.13 Interrupt Signal Input Timing................................................................................ 794

Figure 24.14 Bus Release Timing .............................................................................................. 794

Figure 24.15 Pin Drive Timing at Standby................................................................................. 795

Figure 24.16

IRQOUT Output Delay Time................................................................................ 795

Figure 24.17 Basic Bus Cycle (No Wait) ................................................................................... 798

Figure 24.18 Basic Bus Cycle (One Software Wait) .................................................................. 799

Figure 24.19 Basic Bus Cycle (One External Wait) ................................................................... 800

Figure 24.20 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM bit = 0),

No Idle Cycle Setting) .......................................................................................... 801

Figure 24.21 Burst ROM Read Cycle (One Access Wait, One External Wait,

One Burst Wait, Two Bursts)................................................................................ 802

Figure 24.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,

CAS Latency

= 2, TRCD = 1 Cycle, TRP = 1 Cycle)........................................... 803

Figure 24.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,

CAS Latency

= 2, TRCD = 2 Cycle, TRP = 2 Cycle)........................................... 804

Figure 24.24 Synchronous DRAM Burst Read Bus Cycle (Single Read

× 4),

(Auto Precharge, CAS Latency

= 2, TRCD = 1 Cycle, TRP = 2 Cycle)............... 805

Figure 24.25 Synchronous DRAM Burst Read Bus Cycle (Single Read

× 4),

(Auto Precharge, CAS Latency

= 2, TRCD = 2 Cycle, TRP = 1 Cycle)............... 806

Figure 24.26 Synchronous DRAM Single Write Bus Cycle

(Auto Precharge, TRWL = 2 Cycle) ..................................................................... 807

Figure 24.27 Synchronous DRAM Single Write Bus Cycle

(Auto Precharge, TRCD

= 3 Cycle, TRWL = 2 Cycle) ........................................ 808

Figure 24.28 Synchronous DRAM Burst Write Bus Cycle (Single Write

× 4),

(Auto Precharge, TRCD

= 1 Cycle, TRWL = 2 Cycle) ........................................ 809

Figure 24.29 Synchronous DRAM Burst Write Bus Cycle (Single Write

× 4),

(Auto Precharge, TRCD

= 2 Cycle, TRWL = 2 Cycle) ........................................ 810

Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (Single Read

× 4)

(Bank Active Mode, ACTV + READ Commands, CAS Latency = 2,

TRCD = 1 Cycle).................................................................................................. 811

Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (Single Read

× 4)

(Bank Active Mode, READ Command, Same Row Address,

CAS Latency = 2, TRCD = 1 Cycle) .................................................................... 812

Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (Single Read

× 4)

(Bank Active Mode, PRE + ACTV + READ Commands,

Different Row Address, CAS Latency = 2, TRCD = 1 Cycle) ............................. 813

SH7713 Datasheet(PDF) 32 Page - Renesas Technology Corp

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