SH7713 datasheet(17/904 Pages) RENESAS

17 / 904 page

Rev.1.50 Aug. 30, 2006 Page xvii of xl

11.7.1 Watchdog Timer Counter (WTCNT).................................................................... 324

11.7.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 324

11.7.3 Notes on Register Access...................................................................................... 326

11.8

Using WDT........................................................................................................................ 327

11.8.1 Canceling Standbys............................................................................................... 327

11.8.2 Changing Frequency ............................................................................................. 328

11.8.3 Using Watchdog Timer Mode .............................................................................. 328

11.8.4 Using Interval Timer Mode .................................................................................. 328

11.9

Notes on Board Design ...................................................................................................... 329

Section 12 Bus State Controller (BSC)..............................................................331

12.1

Features.............................................................................................................................. 331

12.2

Input/Output Pins ...............................................................................................................334

12.3

Area Overview ...................................................................................................................336

12.3.1 Area Division........................................................................................................ 336

12.3.2 Shadow Area......................................................................................................... 336

12.3.3 Address Map ......................................................................................................... 338

12.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 340

12.3.5 Data Alignment..................................................................................................... 340

12.4

Register Descriptions ......................................................................................................... 341

12.4.1 Common Control Register (CMNCR) .................................................................. 342

12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) ..... 345

12.4.3 CSn Space Wait Control Register (CSnWCR)

(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)............................................................................. 351

12.4.4 SDRAM Control Register (SDCR)....................................................................... 378

12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 381

12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 382

12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 383

12.5

Operation ........................................................................................................................... 384

12.5.1 Endian/Access Size and Data Alignment.............................................................. 384

12.5.2 Normal Space Interface......................................................................................... 390

12.5.3 Access Wait Control ............................................................................................. 396

12.5.4

CSn Assert Period Expansion ............................................................................... 398

12.5.5 SDRAM Interface ................................................................................................. 399

12.5.6 Burst ROM (Clock Asynchronous) Interface ....................................................... 440

12.5.7 Byte-Selection SRAM Interface ........................................................................... 442

12.5.8 PCMCIA Interface ................................................................................................ 447

12.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 453

12.5.10 Wait between Access Cycles ................................................................................ 454

12.5.11 Bus Arbitration ..................................................................................................... 454

SH7713 Datasheet(PDF) 17 Page - Renesas Technology Corp

SH7713 Datasheet(HTML) 17 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL